symp
symp
  • Register File Verilog

    See on Github

    Class

    CprE 281
    Digital Logic

  • Date

    2019, November

  • Time Taken

    4 Hours

Info

The Goal of this project was to write the verilog to implement a Register File. This project required five verilog modules including a decoder, a D flip-flop, and a multiplexer. By far the most challenging part was connecting all of the modules to make a functional register file.